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industrial temperature range IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii 1 gl g1 pd a1 a1 a2 g2 a2 sel output control output control output control output control output control output control output control output control output control q2 q2 q1 q1 q3 q3 q4 q4 q5 q5 q6 q6 q7 q7 q8 q8 q9 q9 output control q12 q12 q14 q14 q15 q15 q16 q16 q13 q13 q11 q11 output control output control output control output control output control q10 q10 output control 1 0 fsel october 2003 IDT5T93GL16 industrial temperature range 2.5v lvds 1:16 glitchless clock buffer terabuffer? ii description: the IDT5T93GL16 2.5v differential clock buffer is a user-selectable differ- ential input to sixteen lvds outputs . the fanout from a differential input to sixteen lvds outputs reduces loading on the preceding driver and provides an efficient clock distribution network. the IDT5T93GL16 can act as a translator from a differential hstl, ehstl, lvepecl (2.5v), lvpecl (3.3v), cml, or lvds input to lvds outputs. a single-ended 3.3v / 2.5v lvttl input can also be used to translate to lvds outputs. the redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source. selectable inputs are controlled by sel. during the switchover, the output will disable low for up to three clock cycles of the previously-selected input clock. the outputs will remain low for up to three clock cycles of the newly- selected clock, after which the outputs will start from the newly-selected input. a fsel pin has been implemented to control the switchover in cases where a clock source is absent or is driven to dc levels below the minimum specifications. the IDT5T93GL16 outputs can be asynchronously enabled/disabled. when disabled, the outputs will drive to the value selected by the gl pin. multiple power and grounds reduce noise. the idt logo is a registered trademark of integrated device technology, inc. ? 2003 integrated device technology, inc. dsc-6185/13 features: ? guaranteed low skew < 25ps (max) ? very low duty cycle distortion < 100ps (max) ? high speed propagation delay < 2ns (max) ? up to 650mhz operation ? glitchless input clock switching ? selectable inputs ? hot insertable and over-voltage tolerant inputs ? 3.3v / 2.5v lvttl, hstl, ehstl, lvepecl (2.5v), lvpecl (3.3v), cml, or lvds input interface ? selectable differential inputs to sixteen lvds outputs ? power-down mode ? 2.5v v dd ? available in tqfp and vfqfpn packages applications: ? clock distribution functional block diagram
industrial temperature range 2 IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii pin configurations 30 39 38 37 36 35 34 33 32 31 29 28 27 v dd g 2 a 2 q 12 q 12 q 11 q 11 q 10 q 10 q 9 q 9 v dd a 2 23 24 19 14 15 16 17 18 20 21 22 25 26 48 47 46 45 44 43 42 41 40 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 v dd g 1 q 1 q 1 q 2 q 2 q 3 q 3 q 4 q 4 v dd a 1 a 1 v d d g l n c q 5 q 5 q 6 q 6 q 7 q 7 q 8 q 8 v d d g n d v d d s e l f s e l q 1 6 q 1 6 q 1 5 q 1 5 q 1 4 q 1 4 q 1 3 q 1 3 v d d p d gnd vfqfpn top view
industrial temperature range IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii 3 43 39 38 37 36 35 34 33 45 44 42 41 40 46 48 47 gnd g 2 a 2 q 12 q 12 q 11 q 11 q 10 q 10 q 9 q 9 v dd a 2 gnd v dd gnd 27 28 29 q 8 n c 23 24 19 17 18 20 21 22 25 26 g n d g l v d d q 5 q 5 q 6 q 6 q 7 q 7 q 8 30 31 32 n c v d d v d d g n d 61 60 59 58 57 56 55 54 53 52 51 50 49 v d d v d d q 1 6 q 1 6 q 1 5 q 1 5 q 1 4 q 1 4 q 1 3 q 1 3 p d f s e l 64 63 62 g n d s e l v d d g n d 11 12 13 v dd a 1 a 1 q 1 q 1 q 2 q 2 q 3 q 3 q 4 q 4 1 2 3 4 5 6 7 8 9 10 gnd g 1 14 15 16 gnd gnd v dd pin configurations (continued) tqfp (1) top view note: 1. 1m/s of airflow is required for tqfp in order to sustain normal operation.
industrial temperature range 4 IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii symbol description max unit v dd power supply voltage ?0.5 to +3.6 v v i input voltage ?0.5 to +3.6 v v o output voltage (2) ?0.5 to v dd +0.5 v t stg storage temperature ?65 to +150 c t j junction temperature 150 c absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. not to exceed 3.6v. symbol parameter min typ. max. unit c in input capacitance ?? 3pf capacitance (1) (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested symbol description min. typ. max. unit t a ambient operating temperature ?40 +25 +85 c v dd internal power supply voltage 2.3 2.5 2.7 v recommended operating range pin description symbol i/o type description a [1:2] i adjustable (1,4) clock input. a [1:2] is the "true" side of the differential clock input. a [1:2] i adjustable (1,4) complementary clock inputs. a [ 1:2] is the complementary side of a [1:2]. for lvttl single-ended operation, a [ 1:2] should be set to the desired toggle voltage for a [1:2] : 3.3v lvttl v ref = 1650mv 2.5v lvttl v ref = 1250mv g 1 i lvttl gate control for differential outputs q 1 and q 1 through q 8 and q 8 . when g 1 is low, the differential outputs are active. when g 1 is high, the differential outputs are asynchronously driven to the level designated by gl (2) . g 2 i lvttl gate control for differential outputs q 9 and q 9 through q 16 and q 16 . when g 2 is low, the differential outputs are active. when g 2 is high, the differential outputs are asynchronously driven to the level designated by gl (2) . gl i lvttl specifies output disable level. if high, "true" outputs disable high and "complementary" outputs disable low. if low, "true" outputs disable low and "complementary" outputs disable high. qn o lvds clock outputs qn o lvds complementary clock outputs sel i lvttl reference clock select. when low, selects a 2 and a 2 . when high, selects a 1 and a 1 . pd i lvttl power-down control. shuts off entire chip. if low, the device goes into low power mode. inputs and outputs are disabled. bo th "true" and "complementary" outputs will pull to v dd . set high for normal operation. (3) fsel i lvttl forces selection of clock input. if high, fsel forces select to the input designated by sel. set low for normal operation. v dd pwr power supply for the device core and inputs gnd pwr ground notes: 1. inputs are capable of translating the following interface standards: single-ended 3.3v and 2.5v lvttl levels differential hstl and ehstl levels differential lvepecl (2.5v) and lvpecl (3.3v) levels differential lvds levels differential cml levels 2. because the gate controls are asynchronous, runt pulses are possible. it is the user's responsibility to either time the gat e control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 3. it is recommended that the outputs be disabled before entering power-down mode. it is also recommended that the outputs rema in disabled until the device completes power- up after asserting pd . 4. the user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.
industrial temperature range IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii 5 dc electrical characteristics over recommended operating range for lvttl (1) symbol parameter test conditions min. typ. (2) max unit input characteristics i ih input high current v dd = 2.7v ? ? 5 a i il input low current v dd = 2.7v ? ? 5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 +3.6 v v ih dc input high 1.7 ? v v il dc input low ? 0.7 v v thi dc input threshold crossing voltage v dd /2 v v ref single-ended reference voltage (3) 3.3v lvttl ? 1.65 ? v 2.5v lvttl ? 1.25 ? notes: 1. see recommended operating range table. 2. typical values are at v dd = 2.5v, +25c ambient. 3. for a [1:2] single-ended operation, a [1:2] is tied to a dc reference voltage. dc electrical characteristics over recommended operating range for differential inputs (1) symbol parameter test conditions m in. typ. (4) max unit input characteristics i ih input high current v dd = 2.7v ? ? 5 a i il input low current v dd = 2.7v ? ? 5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 +3.6 v v dif dc differential voltage (2) 0.1 ? v v cm dc common mode input voltage (3) 0.05 v dd v notes: 1. see recommended operating range table. 2. v dif specifies the minimum input differential voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. the dc differential voltage must be maintained to guarantee retaining the existing high or low input. the ac differential voltage must be achieved to guarantee switching to a new state. 3. v cm specifies the maximum allowable range of (v tr + v cp ) /2. 4. typical values are at v dd = 2.5v, +25c ambient. dc electrical characteristics over recommended operating range for lvds (1) symbol parameter test conditions min. typ. (2) max unit output characteristics v ot (+) differential output voltage for the true binary state 247 ? 454 mv v ot (-) differential output voltage for the false binary state 247 ? 454 mv ? v ot change in v ot between complementary output states ? ? 50 mv v os output common mode voltage (offset voltage) 1.125 1.2 1.375 v ? v os change in v os between complementary output states ? ? 50 mv i os outputs short circuit current v out + and v out - = 0v ? 12 24 ma i osd differential outputs short circuit current v out + = v out -?612ma notes: 1. see recommended operating range table. 2. typical values are at v dd = 2.5v, +25c ambient.
industrial temperature range 6 IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii differential input ac test conditions for lvepecl (2.5v) and lvpecl (3.3v) symbol parameter value units v dif input signal swing (1) 732 mv v x differential input signal crossing point (2) lvepecl 1082 mv lvpecl 1880 d h duty cycle 50 % v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 2 v/ns notes: 1. the 732mv peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ate) environment. this device meets the v dif (ac) specification under actual use conditions. 2. 1082mv lvepecl (2.5v) and 1880mv lvpecl (3.3v) crossing point levels are specified to allow consistent, repeatable results in an automatic test equipment (ate) environment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 2v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. differential input ac test conditions for ehstl symbol parameter value units v dif input signal swing (1) 1v v x differential input signal crossing point (2) 900 mv d h duty cycle 50 % v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 2 v/ns notes: 1. the 1v peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (at e) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a 900mv crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate) envir onment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 2v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. differential input ac test conditions for hstl symbol parameter value units v dif input signal swing (1) 1v v x differential input signal crossing point (2) 750 mv d h duty cycle 50 % v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 2 v/ns notes: 1. the 1v peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (at e) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a 750mv crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate) envir onment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 2v/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
industrial temperature range IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii 7 differential input ac test conditions for lvds symbol parameter value units v dif input signal swing (1) 400 mv v x differential input signal crossing point (2) 1.2 v d h duty cycle 50 % v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 2 v/ns notes: 1. the 400mv peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ate) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a 1.2v crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate) enviro nment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 2v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. power supply characteristics for lvds outputs (1) symbol parameter test conditions typ. max unit i ddq quiescent v dd power supply current v dd = max., all input clocks = low (2) ? 350 ma outputs enabled i tot total power v dd supply current v dd = 2.7v., f reference clock = 650mhz ? 360 ma i pd total power down supply current pd = low ? 5 ma notes: 1. these power consumption characteristics are for all the valid input interfaces and cover the worst case conditions. 2. the true input is held low and the complementary input is held high. ac differential input specifications (1) symbol parameter min. typ. max unit v dif ac differential voltage (2) 0.1 ? 3.6 v v ix differential input crosspoint voltage 0.05 ? v dd v v cm common mode input voltage range (3) 0.05 ? v dd v v in input voltage - 0.3 +3.6 v notes: 1. the output will not change state until the inputs have crossed and the minimum differential voltage defined by v dif has been met or exceeded. 2. v dif specifies the minimum input voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. the ac differential voltage must be achieved to guarantee switching to a new state. 3. v cm specifies the maximum allowable range of (v tr + v cp ) /2.
industrial temperature range 8 IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii ac electrical characteristics over operating range (1,5) symbol parameter min. typ. max unit skew parameters t sk ( o ) same device output pin-to-pin skew (2) ? ? 25 ps t sk ( p ) pulse skew (3) ?? 100 ps t sk ( pp ) part-to-part skew (4) ?? 300 ps propagation delay t plh propagation delay a, a crosspoint to qn, qn crosspoint ? 1.5 2 ns t phl f o frequency range (6) ?? 650 m h z output gate enable/disable delay t pge output gate enable crossing v thi to qn/ qn crosspoint ?? 3.5 ns t pgd output gate disable crossing v thi to qn/ qn crosspoint driven to gl designated level ?? 3.5 ns power down timing t pwrdn pd crossing v thi to qn = v dd , qn = v dd ?? 100 s t pwrup output gate disable crossing v thi to qn/ qn driven to gl designated level ?? 100 s notes: 1. ac propagation measurements should not be taken within the first 100 cycles of startup. 2. skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions a nd load conditions on any one device. 3. skew measured is the difference between propagation delay times t phl and t plh of any single differential output pair under identical input and output interfaces, transitions and load conditions on any one device. 4. skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devi ces, given identical transitions and load conditions at identical v dd levels and temperature. 5. all parameters are tested with a 50% input duty cycle. 6. guaranteed by design but not production tested.
industrial temperature range IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii 9 notes: 1. pulse skew is calculated using the following expression: t sk ( p ) = | t phl - t plh | note that the t phl and t plh shown above are not valid measurements for this calculation because they are not taken from the same pulse. 2. ac propagation measurements should not be taken within the first 100 cycles of startup. t plh t phl t sk(o) t sk(o) qn - qn qm - qm + v dif v dif = 0 - v dif + v dif v dif = 0 - v dif a [1:2] - a [1:2] + v dif v dif = 0 - v dif 1/fo differential ac timing waveforms output propagation and skew waveforms
industrial temperature range 10 IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii differential gate disable/enable showing runt pulse generation note: 1. as shown, it is possible to generate runt pulses on gate disable and enable of the outputs. it is the user's responsibility to time their gx signals to avoid this problem. t plh gl gx qn - qn t pgd t pge v ih v thi v il v ih v thi v il + v dif v dif = 0 - v dif a [1:2] - a [1:2] + v dif v dif = 0 - v dif glitchless output operation with switching input clock selection notes: 1. when sel changes, the output clock goes low on the falling edge of the output clock up to three cycles later. the output t hen stays low for up to three clock cycles of the new input clock. after this, the output starts with the rising edge of the new input clock. 2. ac propagation measurements should not be taken within the first 100 cycles of startup. a 1 - a 1 a 2 - a 2 sel qn - qn + v dif v dif = 0 - v dif + v dif v dif = 0 - v dif v ih v thi v il + v dif v dif = 0 - v dif
industrial temperature range IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii 11 fsel operation for when opposite clock dies notes: 1. when the differential on the selected clock goes below the minimum dc differential, the outputs clock goes to an unknown st ate. when this happens, the sel pin should be toggled and fsel asserted in order to force selection of the new input clock. the output clock will start up after a number of cycles of the newly-selected input clock. 2. the fsel pin should stay asserted until the problem with the dead clock can be fixed in the system. 3. it is recommended that the fsel be tied high for systems that use only one input. if this is not possible, the user must gua rantee that the unused input have a differential greater than or equal to the minimum dc differential specified in the datasheet. fsel operation for when current clock dies notes: 1. when the differential on the non-selected clock goes below the minimum dc differential, the outputs clock goes to an unknow n state. when this happens, the fsel pin should be asserted in order to force selection of the new input clock. the output clock will start up after a number of cycles of the newly-selected input clock. 2. the fsel pin should stay asserted until the problem with the dead clock can be fixed in the system. 3. it is recommended that the fsel be tied high for systems that use only one input. if this is not possible, the user must gua rantee that the unused input have a differential greater than or equal to the minimum dc differential specified in the datasheet. a 1 - a 1 a 2 - a 2 sel v thi v ih v il +v dif v dif =0 -v dif +v dif v dif =0 -v dif +v dif v dif =0 -v dif fsel qn - qn v thi v ih v il a 1 - a 1 a 2 - a 2 sel v thi v ih v il qn - qn +v dif v dif =0 -v dif fsel v thi v ih v il +v dif v dif =0 -v dif +v dif v dif =0 -v dif
industrial temperature range 12 IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii selection of input while protecting against when opposite clock dies notes: 1. if the user holds fsel high, the output will not be affected by the deselected input clock. 2. the output will immediately be driven to low once fsel is asserted. this may cause glitching on the output. the output will restart with the input clock selected by the sel pin. 3. if the user decides to switch input clocks, the user must de-assert fsel, then assert fsel after toggling the sel input pin. the output will be driven low and will restart with the input clock selected by the sel pin. a 2 - a 2 a 1 - a 1 fsel v thi v ih v il +v dif v dif =0 -v dif v thi v ih v il +v dif v dif =0 -v dif +v dif v dif =0 -v dif qn - qn sel fsel operation to protect against when opposite clock dies notes: 1. if the user holds fsel high, the output will not be affected by the deselected input clock. 2. the output will immediately be driven to low once fsel is asserted. this may cause glitching on the output. the output will restart with the input clock selected by the sel pin. 3. if the user decides to switch input clocks, the user must de-assert fsel, then assert fsel after toggling the sel input pin. the output will be driven low and will restart with the input clock selected by the sel pin. a 1 - a 1 a 2 - a 2 sel v thi v ih v il qn - qn +v dif v dif =0 -v dif fsel v thi v ih v il +v dif v dif =0 -v dif +v dif v dif =0 -v dif
industrial temperature range IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii 13 power down timing notes: 1. it is recommended that outputs be disabled before entering power-down mode. it is also recommended that the outputs remain d isabled until the device completes power-up after asserting pd . 2. the power down timing diagram assumes that gl is high. 3. it should be noted that during power-down mode, the outputs are both pulled to v dd . in the power down timing diagram this is shown when qn - qn goes to v dif = 0. gx qn - qn +v dif v dif =0 - v dif +v dif v dif =0 -v dif +v dif v dif =0 -v dif pd a 1 - a 1 a 2 - a 2 v thi v ih v il v thi v ih v il
industrial temperature range 14 IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii test circuits and conditions v dd /2 d.u.t. a a pulse generator ~50 ? transmission line ~50 ? transmission line v in v in -v dd /2 scope 50 ? 50 ? test circuit for differential input differential input test conditions symbol v dd = 2.5v 0.2v unit v thi crossing of a and a v
industrial temperature range IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii 15 v dd d.u.t. a a qn qn pulse generator r l r l v os v od v dd /2 d.u.t. a a qn qn pulse generator 50 ? 50 ? z = 50 ? z = 50 ? scope c l -v dd /2 c l test circuit for dc outputs and power down tests test circuit for propagation, skew, and gate enable/disable timing notes: 1. specifications only apply to "normal operations" test condition. the t ia /e ia specification load is for reference only. 2. the scope inputs are assumed to have a 2pf load to ground. t ia /e ia - 644 specifies 5pf between the output pair. with c l = 8pf, this gives the test circuit appropriate 5pf equivalent load. lvds output test condition symbol v dd = 2.5v 0.2v unit c l 0 (1) pf 8 (1,2) r l 50 ?
industrial temperature range 16 IDT5T93GL16 2.5v lvds 1:16 glitchless clock buffer terabuffer ii ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xxxxx package device type 5t93gl16 2.5v lvds 1:16 glitchless clock buffer terabuffer? ii thin quad flat pack thermally enhanced plastic very fine pitch quad flat no lead package tf nl xx process x -40c to +85c (industrial) i

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